仿真结果
1 module sdram_init
2 (
3 input sys_clk , //100Mhz
4 input sys_rst_n ,
5
6 output reg [3:0] init_cmd , //init_cmd {cs# , ras# , cas# , we# }
7 output reg [1:0] init_ba , //select logic bank
8 output reg [12:0] init_addr , //
9 output reg init_end
10 );
11
12 //~~~~~~~~~~~~~~~~~~~~~~~~~~~reg/wire~~~~~~~~~~~~~~~~~~~~
13
14
15
16 reg [7:0] current_state; //
17 reg [7:0] next_state; //
18 reg [15:0] cnt_200us; //
19 reg wait_end; //
20 reg trp_end; //
21 reg trfc_end; //
22 reg tmrd_end; //
23 reg [3:0] cnt_clk; //
24 reg [3:0] cnt_ar;
25
26
27
28 //~~~~~~~~~~~~~~~~~~~~~~~~~~~localparam~~~~~~~~~~~~~~~~~~~~
29
30
31 localparam INIT_IDLE = 8'b0000_0001 ;
32 localparam INIT_PRE = 8'b0000_0010 ;
33 localparam INIT_TRP = 8'b0000_0100 ;
34 localparam INIT_AR = 8'b0000_1000 ;
35 localparam INIT_TRFC = 8'b0001_0000 ;
36 localparam INIT_MRS = 8'b0010_0000 ;
37 localparam INIT_TMRD = 8'b0100_0000 ;
38 localparam INIT_END = 8'b1000_0000 ;
39
40
41
42 localparam CNT_200US_MAX = 12'd20000 ;
43 localparam CNT_TRP = 4'd3 ;
44 localparam CNT_TRFC = 4'd10 ;
45 localparam CNT_TMRD = 4'd2 ;
46
47
48 //init_cmd {cs# , ras# , cas# , we# }
49 localparam NOP = 4'b0111 ;
50 localparam P_CHARGE = 4'b0010 ;
51 localparam AUTO_REF = 4'b0001 ;
52 localparam M_REG_SET = 4'b000 ;
53
54
55 //~~~~~~~~~~~~~~~~~~~~~~~~~~~fsm~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
56
57 always@(posedge sys_clk or negedge sys_rst_n)
58 if(!sys_rst_n)
59 current_state <= INIT_IDLE;
60 else
61 current_state <= next_state;
62
63
64 always@(*)
65 begin
66 case(current_state)
67
68 INIT_IDLE : if(wait_end == 1'b1)
69 next_state <= INIT_PRE;
70 else
71 next_state <= INIT_IDLE;
72
73 INIT_PRE : next_state <= INIT_TRP;
74
75 INIT_TRP : if(trp_end == 1'b1)
76 next_state <= INIT_AR;
77 else
78 next_state <= INIT_TRP;
79
80 INIT_AR : next_state <= INIT_TRFC;
81
82 INIT_TRFC : if(trfc_end == 1'b1)
83 begin
84 if(cnt_ar == 4'd8)
85 next_state <= INIT_MRS;
86 else
87 next_state <= INIT_AR;
88 end
89 else
90 next_state <= INIT_TRFC;
91
92 INIT_MRS : next_state <= INIT_TMRD;
93
94 INIT_TMRD : if(tmrd_end == 1'b1)
95 next_state <= INIT_END;
96 else
97 next_state <= INIT_TMRD;
98 INIT_END : next_state <= INIT_END;
99
100 default : next_state <= INIT_IDLE;
101
102 endcase
103
104 end
105
106
107
108
109 //~~~~~~~~~~~~~~~~~~~~~~~~~~~cnt~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
110 //-----------cnt_200us
111 always@(posedge sys_clk or negedge sys_rst_n)
112 if(!sys_rst_n)
113 cnt_200us <= 16'd0;
114 else if(current_state == INIT_IDLE)
115 begin
116 if(cnt_200us < 16'd20000)
117 cnt_200us <= cnt_200us + 12'd1;
118 else
119 cnt_200us <= 16'd0;
120 end
121 else
122 cnt_200us <= 16'd0;
123
124
125 //-----------wait_end
126 always@(posedge sys_clk or negedge sys_rst_n)
127 if(!sys_rst_n)
128 wait_end <= 1'd0;
129 else if(cnt_200us == 16'd20000)
130 wait_end <= 1'd1;
131 else
132 wait_end <= 1'd0;
133
134 //-----------cnt_clk
135 always@(posedge sys_clk or negedge sys_rst_n)
136 if(!sys_rst_n)
137 cnt_clk <= 4'd0;
138 else if(current_state == INIT_TRP)
139 begin
140 if(cnt_clk < CNT_TRP)
141 cnt_clk <= cnt_clk + 1'b1;
142 else
143 cnt_clk <= 4'd0;
144 end
145 else if(current_state == INIT_TRFC)
146 begin
147 if(cnt_clk < CNT_TRFC)
148 cnt_clk <= cnt_clk + 1'b1;
149 else
150 cnt_clk <= 4'd0;
151 end
152 else if(current_state == INIT_TMRD)
153 begin
154 if(cnt_clk < CNT_TMRD)
155 cnt_clk <= cnt_clk + 1'b1;
156 else
157 cnt_clk <= 4'd0;
158 end
159 else
160 cnt_clk <= 4'd0;
161
162 //-----------trp_end
163 always@(posedge sys_clk or negedge sys_rst_n)
164 if(!sys_rst_n)
165 trp_end <= 1'd0;
166 else if((current_state == INIT_TRP)&&(cnt_clk == CNT_TRP))
167 trp_end <= 1'd1;
168 else
169 trp_end <= 1'd0;
170
171 //-----------trfc_end
172 always@(posedge sys_clk or negedge sys_rst_n)
173 if(!sys_rst_n)
174 trfc_end <= 1'd0;
175 else if((current_state == INIT_TRFC)&&(cnt_clk == CNT_TRFC))
176 trfc_end <= 1'd1;
177 else
178 trfc_end <= 1'd0;
179
180 //-----------tmrd_end
181 always@(posedge sys_clk or negedge sys_rst_n)
182 if(!sys_rst_n)
183 tmrd_end <= 1'd0;
184 else if((current_state == INIT_TMRD)&&(cnt_clk == CNT_TMRD))
185 tmrd_end <= 1'd1;
186 else
187 tmrd_end <= 1'd0;
188
189 //-----------cnt_ar
190 always@(posedge sys_clk or negedge sys_rst_n)
191 if(!sys_rst_n)
192 cnt_ar <= 4'd0;
193 else if((current_state == INIT_TRFC)&&(cnt_clk == CNT_TRFC))
194 cnt_ar <= cnt_ar + 1'd1;
195 else
196 cnt_ar <= cnt_ar;
197
198
199 //~~~~~~~~~~~~~~~~~~~~~~~~~~~output~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
200
201 always@(posedge sys_clk or negedge sys_rst_n)
202 if(!sys_rst_n)
203 begin
204 init_cmd <= NOP ;
205 init_ba <= 2'b11 ;
206 init_addr <= 13'h1fff ;
207 init_end <= 1'b0 ;
208 end
209 else if(current_state == INIT_IDLE)
210 begin
211 init_cmd <= NOP ;
212 init_ba <= 2'b11 ;
213 init_addr <= 13'h1fff ;
214 init_end <= 1'b0 ;
215 end
216 else if(current_state == INIT_PRE)
217 begin
218 init_cmd <= P_CHARGE ;
219 init_ba <= 2'b11 ;
220 init_addr <= 13'h1fff ;
221 init_end <= 1'b0 ;
222 end
223 else if(current_state == INIT_TRP)
224 begin
225 init_cmd <= NOP ;
226 init_ba <= 2'b11 ;
227 init_addr <= 13'h1fff ;
228 init_end <= 1'b0 ;
229 end
230 else if(current_state == INIT_AR)
231 begin
232 init_cmd <= AUTO_REF ;
233 init_ba <= 2'b11 ;
234 init_addr <= 13'h1fff ;
235 init_end <= 1'b0 ;
236 end
237 else if(current_state == INIT_TRFC)
238 begin
239 init_cmd <= NOP ;
240 init_ba <= 2'b11 ;
241 init_addr <= 13'h1fff ;
242 init_end <= 1'b0 ;
243 end
244 else if(current_state == INIT_MRS)
245 begin
246 init_cmd <= M_REG_SET ;
247 init_ba <= 2'b00 ;
248 init_addr <= {
249 3'b000 , //A12-A10:预留
250 1'b0 , //A9=0:读写方式,0:突发读&突发写,1:突发读&单写
251 2'b00 , //{A8,A7}=00:标准模式,默认
252 3'b011 , //{A6,A5,A4}=011:CAS 潜伏期,010:2,011:3,其他:保留
253 1'b0 , //A3=0:突发传输方式,0:顺序,1:隔行
254 3'b111 //{A2,A1,A0}=111:突发长度,000:单字节,001:2 字节
255 } ;
256 init_end <= 1'b0 ;
257 end
258 else if(current_state == INIT_TMRD)
259 begin
260 init_cmd <= NOP ;
261 init_ba <= 2'b11 ;
262 init_addr <= 13'h1fff ;
263 init_end <= 1'b0 ;
264 end
265 else if(current_state == INIT_END)
266 begin
267 init_cmd <= NOP ;
268 init_ba <= 2'b11 ;
269 init_addr <= 13'h1fff ;
270 init_end <= 1'b1 ;
271 end
272 else
273 begin
274 init_cmd <= init_cmd ;
275 init_ba <= init_ba ;
276 init_addr <= init_addr ;
277 init_end <= init_end ;
278 end
279
280
281
282
283
284
285 endmodule
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