VCS仿真 Dump Memory

---

两种方法

• vcs联合verdi生成fsdb文件
• vcs生成vpd文件

VCS联合verdi生成fsdb文件

1.testbench中加入如下语句：

initial begin

     $fsdbDumpfile("tb.fsdb");

     $fsdbDumpvars;

end

always@(posedge clk)

begin

  $fsdbDumpMDA(R1); //每个时钟dump出mem的值，verdi记录值的变化

  $fsdbDumpMDA(R2);

end

2.注意调用 vcs -debug_pp 开始仿真

3.测试使用的verilog代码与仿真脚本

testbench

`timescale 1ns/100ps

module Testbench;

  reg          clk;

  integer      i;

  reg          R1[7:0];

  reg [3:0]    R2[7:0];

  initial  begin

    clk = 0;  

	for (i=0; i<8; i=i+1) begin

	  R1[i] = 1'b0;

	  R2[i] = 4'h0;

	end

	#10;

	for (i=0; i<8; i=i+1) begin

	  R1[i] = $random;

	  R2[i] = $random;

	end

    repeat(5) @(posedge clk);

	for (i=0; i<8; i=i+1) begin

	  R1[i] = $random;

	  R2[i] = $random;

	end

    repeat(60) @(posedge clk);

    $finish;

  end

always #200 clk = ~clk;

initial begin

     $fsdbDumpfile("tb.fsdb");

     $fsdbDumpvars;

end

always@(posedge clk)

begin

  $fsdbDumpMDA(R1); //每个时钟dump出mem的值，verdi记录值的变化

  $fsdbDumpMDA(R2);

end

endmodule

注意:此处仅是示范dumpMemory，实际中需要每一个时钟沿都需dump数据

vcs仿真脚本

#!/bin/bash -f

export NOVAS_HOME="/EDA/Synopsys/verdi/vJ-2014.12-SP2"

export NOVAS_PLI="${NOVAS_HOME}/share/PLI/VCS/LINUX64"

export LD_LIBRARY_PATH="$NOVAS_PLI"

export NOVAS="${NOVAS_HOME}/share/PLI/VCS/LINUX64"

export novas_args="-P $NOVAS/novas.tab   $NOVAS/pli.a "

vcs +v2k -sverilog +vcs+lic+wait -full64 -debug_pp \

       +warn=noCDNYI,noIPDW,noILLGO,noTMR,noPHNE,noIRIID-W \

       -Mupdate +notimingcheck +nospecify \

       ${novas_args}\

       -f file.f \

./simv

4.使用Verdi查看结果

verdi 打开波形文件，选择>>Tool>>Memory/MDA

5.截图(verdi)

vcs生成vpd文件

1.lab文件

testbench

`timescale 1ns/100ps

module Testbench;

  reg          clk;

  integer      i;

  reg          R1[7:0];

  reg [3:0]    R2[7:0];

  initial  begin

    clk = 0;  

	for (i=0; i<8; i=i+1) begin

	  R1[i] = 1'b0;

	  R2[i] = 4'h0;

	end

	#10;

	for (i=0; i<8; i=i+1) begin

	  R1[i] = $random;

	  R2[i] = $random;

	end

    repeat(5) @(posedge clk);

	for (i=0; i<8; i=i+1) begin

	  R1[i] = $random;

	  R2[i] = $random;

	end

    repeat(60) @(posedge clk);

    $finish;

  end

always #200 clk = ~clk;

initial begin

  $vcdpluson();

end

always@(posedge clk)

begin

    $vcdplusmemon();

end

endmodule

vcs脚本

vcs -full64 Testbench.v  -debug_pp +vcd+vcdpluson

./simv

2.截图(dve)

参考文献

http://www.edaboard.com/thread59624.html

verdi3手册