`timescale 1ns / 1ps

 module FSM(

     clk,rst_n,

     in1,in2,

     out1,out2,

     CS,NS

     );

      input clk,rst_n;

      input in1,in2;

      output out1,out2;

      output [:] CS,NS;

      reg [:] CS,NS;

      reg out1,out2;

      parameter       St0 = 'b00,

                         St1 = 'b01,

                         St2 = 'b10,

                         St3 = 'b11;

      // 1、状态切换

      always @(posedge clk or negedge rst_n)

      if(!rst_n)

      begin

         CS<=St0;

      end

      else

         CS<=NS;

     // 2、次态转移

     always @ (*)

     begin

         case(CS)

             St0:

             begin

                 if(in1=='b1) NS=St1;

                 else NS=St0;

             end

             St1:

             begin

                 NS=St2;

             end

             St2:

             begin

                 NS=St3;

             end

             St3:

             begin

                 if(in2=='b1) NS=St0;

                 else NS=St3;

             end

             default:NS=St0;

         endcase

     end

     //3、输出逻辑

     always @(*)

     begin

     if(CS==St1) out1='b1;

     else out1='b0;

     if(CS==St2) out2='b1;

     else out2='b0;

     end

 endmodule