IQ失衡问题。
1首先用matlab生成输入信号计算b矩阵，达到收敛。
2再导出输入信号作为fpga的输入，在vivado上进行仿真，计算的b矩阵应与matlab计算一致。
3导出真实信号作为输入，在matlab中计算，可能存在直流偏移需要滤除。
4真实信号在vivado上仿真测试。
5上板测试

下面为组合逻辑实现代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/09/16 20:57:52
// Design Name: 
// Module Name: iq
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module iq(
	input adsp_clk,//10M
	input refclk,//100M
	input refclk2, //10M
	output signed [31:0]I_out,
	output signed [31:0]Q_out,
	input signed [13:0]sin_coe,
	input signed [13:0]cos_coe,
	output signed [31:0]b11_out,
	output signed [31:0]b12_out,
	output signed [31:0]b21_out,
	output signed [31:0]b22_out,
	output signed [31:0]yi1_out,
	output signed [31:0]yq1_out,
	output signed [13:0]yi,
	output signed [13:0]yq
	
    );
	reg signed [31:0] b11=32'sb00010000000000000000000000000000,b12=32'sb00000000000000000000000000000000,b21=32'sb00000000000000000000000000000000,b22=32'sb00010000000000000000000000000000;
	reg signed [31:0] a =32'sb00000000000000000000010000000000;
	reg signed [31:0]I_chanel_reg,Q_chanel_reg;
	reg signed [31:0] yi1,yq1;
	reg signed [31:0] one =32'sb00010000000000000000000000000000;
	reg signed [31:0] yi12,yq12;
	reg signed [31:0] test1=32'sb00000000000000000000000000000000,test2=32'sb00000000000000000000000000000000,test3=32'sb00000000000000000000000000000000,test4=32'sb00000000000000000000000000000000;
	//b11={b11[15],b11[0]<<14};
	//b12={b12[15],b12[0]<<14};
	//b21={b21[15],b21[0]<<14};
	//b22={b22[15],b22[0]<<14};
	reg [17:0]addr=0;
	reg signed[31:0] b11_t,b12_t,b21_t,b22_t;
	wire signed [31:0]sin_wr,cos_wr;
	reg signed [31:0] yi1_2,yi1_4,yq1_2,yq1_4,yi1_31,yq1_31,yiq_1;
	reg signed [31:0]onea=32'sb00010000000000000000010000000000;
	reg signed[31:0] b11_p,b12_p,b21_p,b22_p;
	
	/*
always@(posedge refclk)
begin
if (!rst)
	addr <= 0;                                  //复位地址清零
else 
	addr <= addr + 1;                           //地址自增
end
	*/



	function signed [31:0] factorial;
		input signed [31:0] operand1,operand2; 
		reg signed [63:0] mult1;
		reg signed [35:0] mult2;
		
		begin
				mult1=operand1*operand2;
				mult2=mult1>>28;
				factorial={mult2[35],mult2[30:0]};
		end
		
	endfunction 
 /*
  always@(posedge refclk2	)
  begin
	yi1<=factorial(b11,{{3{cos_coe[19]}},cos_coe[18:0]})+factorial(b12,{{3{sin_coe[19]}},sin_coe[18:0]});
	yq1<=factorial(b21,{{3{cos_coe[19]}},cos_coe[18:0]})+factorial(b22,{{3{sin_coe[19]}},sin_coe[18:0]});


	
  end
 
 */
 
 
  always @(posedge adsp_clk)
begin
#10
	yi1=factorial(b11,{{3{sin_coe[13]}},sin_coe[12:0],16'b0000000000})+factorial(b12,{{3{cos_coe[13]}},cos_coe[12:0],16'b0000000000});
	yq1=factorial(b21,{{3{sin_coe[13]}},sin_coe[12:0],16'b0000000000})+factorial(b22,{{3{cos_coe[13]}},cos_coe[12:0],16'b0000000000});
	
	yi1_2=factorial(yi1,yi1);
	yq1_2=factorial(yq1,yq1);
	yq1_4=factorial(yq1_2,yq1_2);
	yi1_4=factorial(yi1_2,yi1_2);
	yiq_1=factorial(yi1,yq1);
	yi1_31=factorial(yi1_2,yiq_1);
	yq1_31=factorial(yq1_2,yiq_1);
	
	b11_t=factorial(a,yi1_4);
	b12_t=factorial(a,yi1_31);
	b21_t=factorial(a,yq1_4);
	b22_t=factorial(a,yq1_31);
	
	
	b11_p=factorial(onea,b11)-factorial(b11_t,b11)-factorial(b12_t,b21);
	b12_p=factorial(onea,b12)-factorial(b11_t,b12)-factorial(b12_t,b22);
	b21_p=factorial(onea,b21)-factorial(b21_t,b21)-factorial(b22_t,b11);
	b22_p=factorial(onea,b22)-factorial(b21_t,b22)-factorial(b22_t,b12);
	b11=b11_p;
	b12=b12_p;
	b21=b21_p;
	b22=b22_p;
	
/*
	yi1=factorial(b11,I_chanel_reg)+factorial(b12,Q_chanel_reg);
	yq1=factorial(b21,I_chanel_reg)+factorial(b22,Q_chanel_reg);

	test1=factorial(yi1,yi1);
	test1=factorial(test1,yi1);
	test2=factorial(test1,yq1);
	test1=factorial(test1,yi1);
	test3=factorial(yq1,yq1);
	test3=factorial(test3,yq1);
	test4=factorial(test3,yi1);
	test3=factorial(test3,yq1);
	
	b11_t=factorial(a,test1);//yi^4
	b12_t=factorial(a,test2);//yi^3*yq
	b21_t=factorial(a,test3);//yq^4
	b22_t=factorial(a,test4);//yq^3*yi


	b11_p=factorial((one+a),b11)-factorial(b11_t,b11)-factorial(b12_t,b21);
	b12_p=factorial((one+a),b12)-factorial(b11_t,b12)-factorial(b12_t,b22);
	b21_p=factorial((one+a),b21)-factorial(b21_t,b21)-factorial(b22_t,b11);
	b22_p=factorial((one+a),b22)-factorial(b21_t,b22)-factorial(b22_t,b12);
	b11=b11_p;
	b12=b12_p;
	b21=b21_p;
	b22=b22_p;
*/
end 





assign I_out=sin_coe;
assign Q_out=cos_coe;
//assign yi1_out={{3{sin_coe[19]}},sin_coe[18:0]};
//assign yq1_out={{3{cos_coe[19]}},cos_coe[18:0]};
assign yi1_out=yi1;
assign yq1_out=yq1;
assign b11_out=b11;
assign b12_out=b12;
assign b21_out=b21;
assign b22_out=b22;
assign yi={yi1[31],yi1[28:16]};
assign yq={yq1[31],yq1[28:16]};

endmodule