开发工具：Quartus II 9.1；
仿真软件：Questa Sim 10.0c；
硬件平台：Terasic DE2-115(EP2C35F672C6)；
外设：MAX3232；
3个工程文件："uart_baud.v" + "uart_rx.v" + "uart_tx.v"；
2个仿真文件::"uart_rx_tsb.v" + "uart_tx_tsb.v"
设计思路：略
注意事项：波特率模块采样脉冲式分频；
接收模块仅在一个时刻采样，若需要考虑误码率可在状态机里插入0-1计数器；
partI:uart_baud.v
`timescale ns / ps
`define SYS_CLK
`define BAUD
`define DIV `SYS_CLK/`BAUD/
module uart_baud(
sys_clk,
sys_rst_n,
sys_baud16_o,
sys_baud_o
);
input sys_clk;
input sys_rst_n;
output sys_baud16_o;
output sys_baud_o; reg [:] baud16_cnt =; always @ (posedge sys_clk) begin
if('b0 == sys_rst_n) baud16_cnt <= 0;
else if(baud16_cnt == `DIV-) baud16_cnt <= ;
else baud16_cnt <= baud16_cnt + 'd1;
end reg [:] baud_cnt = ;
always @ (posedge sys_clk) begin
if('b0 == sys_rst_n) baud_cnt <= 0;
else if(sys_baud16_o == 'b1) baud_cnt <= baud_cnt + 1'd1;
else baud_cnt <= baud_cnt;
end assign sys_baud16_o = (baud16_cnt == `DIV-)?'b1:1'b0;
assign sys_baud_o = ((baud_cnt == 'd15) && (sys_baud16_o == 1'b1))?'b1:1'b0; endmodule
partII:uart_tx.v
`timescale ns / ps
`define SIM
module uart_tx(
sys_clk,
sys_rst_n,
sys_baud_i,
sys_wreq_i,
sys_data_i,
uart_tx,
uart_tx_idle_o,
uart_tx_ack_o
);
input sys_clk;
input sys_rst_n;
input sys_baud_i;
input sys_wreq_i;
input [:] sys_data_i;
output uart_tx;
output uart_tx_idle_o;
output uart_tx_ack_o;
`ifdef SIM
parameter ST_WIDTH = ;
parameter IDLE = "IDLE.",
START = "START",
SHIFT = "SHIFT",
CHECK = "CHECK",
END = "END..";
`else
parameter ST_WIDTH = ;
parameter IDLE = 'b0_0001,
START = 'b0_0010,
SHIFT = 'b0_0100,
CHECK = 'b0_1000,
END = 'b1_0000;
`endif
parameter EVEN = 'd0; reg [ST_WIDTH-:] c_st = IDLE;
reg [ST_WIDTH-:] n_st = IDLE;
reg check_bit = ; //奇偶检验位
reg [:] bit_cnt = ; //计数8个比特
reg uart_tx=; always @ (posedge sys_clk) begin
if(sys_rst_n == 'b0) c_st <= IDLE;
else c_st <= n_st;
end always @ (*) begin
n_st = IDLE;
case(c_st)
IDLE:begin
n_st = ('b1 == sys_wreq_i)?START:IDLE;end
START:begin
n_st = (sys_baud_i == 'b1)?SHIFT:START;end
SHIFT:begin
n_st = ((bit_cnt == 'd7) && (sys_baud_i == 1'b1))?CHECK:SHIFT;end
CHECK:begin
n_st = (sys_baud_i == 'b1)?END:CHECK;end
END:begin
n_st = (sys_baud_i == 'b1)?IDLE:END;end
default:begin
n_st = IDLE;end
endcase
end always @ (posedge sys_clk) begin
if('b0 == sys_rst_n) begin
bit_cnt <= 'd7;
uart_tx <= ;
check_bit <= EVEN;
end
else begin
case(n_st)
IDLE:begin
bit_cnt <= 'd7;
uart_tx <= ;
check_bit <= EVEN;end
START:begin
bit_cnt <= 'd7;
uart_tx <= ;
check_bit <= EVEN;end
SHIFT:begin
uart_tx <= sys_data_i[bit_cnt];
check_bit <= (sys_baud_i == 'b1)?check_bit^sys_data_i[bit_cnt]:check_bit;
bit_cnt <= (sys_baud_i == 'b1)?bit_cnt + 1'd1:bit_cnt;end
CHECK:begin
uart_tx <= check_bit;
check_bit <= check_bit;
bit_cnt <= 'd7;end
END:begin
bit_cnt <= 'd7;
check_bit <= check_bit;
uart_tx <= ;end
default:begin
bit_cnt <= bit_cnt;
check_bit <= check_bit;
uart_tx <= uart_tx;end
endcase
end
end //assign
assign uart_tx_idle_o = (c_st == IDLE)?'b1:1'b0;
assign uart_tx_ack_o = ((c_st == END) && (sys_baud_i == 'b1))?1'b1:'b0; endmodule
partIII:uart_rx.v
`timescale ns / ps
`define SIM
module uart_rx(
sys_clk,
sys_rst_n,
uart_rx,
sys_baud16_i,
uart_rx_idle_o,
uart_rx_ack_o,
uart_rx_error_o,
sys_data_o
);
input sys_clk;
input sys_rst_n;
input uart_rx;
input sys_baud16_i;
output uart_rx_idle_o;
output uart_rx_ack_o;
output uart_rx_error_o;
output [:] sys_data_o;
parameter EVEN = 'd0;
`ifdef SIM
parameter ST_WIDTH = ;
parameter IDLE = "IDLE.",
START = "START",
SHIFT = "SHIFT",
CHECK = "CHECK",
END = "END..";
`else
parameter ST_WIDTH = ;
parameter IDLE = 'b0_0001,
START = 'b0_0010,
SHIFT = 'b0_0100,
CHECK = 'b0_1000,
END = 'b1_0000;
`endif //capture the negedge of rx
reg rx_r0=;
wire rx_trigger; always @ (posedge sys_clk) begin
if('b0 == sys_rst_n) rx_r0 <= 1;
else if('b1 == sys_baud16_i) rx_r0 <= uart_rx;
else rx_r0 <= rx_r0;
end assign rx_trigger = ~uart_rx & rx_r0; //fsm
reg [ST_WIDTH-:] c_st = IDLE;
reg [ST_WIDTH-:] n_st = IDLE;
reg [:] bit_cnt = 'd0;
reg [:] clk_cnt = 'd0;
reg [:] sys_data = 'd0;
reg check_bit = EVEN;
reg error = ;
//fsm-1
always @ (posedge sys_clk) begin
if(sys_rst_n == 'b0) c_st <= IDLE;
else c_st <= n_st;
end
//fsm-2
always @ (*) begin
n_st = IDLE;
case(c_st)
IDLE:begin
n_st = (rx_trigger == 'b1)?START:IDLE;end
START:begin
n_st = (clk_cnt == 'd15 && sys_baud16_i == 1'b1)?SHIFT:START;end
SHIFT:begin
n_st = ((clk_cnt == 'd15)&&(bit_cnt == 4'd8))?CHECK:SHIFT;end
CHECK:begin
n_st = (clk_cnt == 'd15 && bit_cnt == 4'd9)?END:CHECK;end
END:begin
n_st = (clk_cnt == 'd15 && bit_cnt == 4'd10)?IDLE:END;end
default:begin
n_st = IDLE;end
endcase
end
//fsm-3
always @ (posedge sys_clk) begin
if(sys_rst_n == 'b0) begin
sys_data <= 'd0;
error <= ;
clk_cnt <= 'd0;
bit_cnt <= 'd0;
check_bit <= EVEN;end
else begin
case(n_st)
IDLE:begin
sys_data <= sys_data;
error <= ;
clk_cnt <= 'd0;
bit_cnt <= 'd0;
check_bit <= EVEN;end
START:begin
sys_data <= sys_data;
error <= ;
clk_cnt <= (sys_baud16_i == 'b1)?(clk_cnt+1'd1):clk_cnt;
bit_cnt <= 'd0;
check_bit <= EVEN;end
SHIFT:begin
sys_data <= ((sys_baud16_i == 'b1)&&(clk_cnt == 4'd15))?{uart_rx,sys_data[:]}:sys_data;
error <= ;
clk_cnt <= (sys_baud16_i)?clk_cnt+'d1:clk_cnt;
bit_cnt <= ((sys_baud16_i)&&(clk_cnt == 'd15))?bit_cnt+1'd1:bit_cnt;
check_bit <= ((sys_baud16_i)&&(clk_cnt == 'd15))?check_bit^sys_data[bit_cnt]:check_bit;end
CHECK:begin
sys_data <= sys_data;
error <= ((sys_baud16_i)&&(clk_cnt == 'd15)&&(uart_rx!=check_bit))?1'b1:error;
clk_cnt <= (sys_baud16_i)?clk_cnt+'d1:clk_cnt;
bit_cnt <= ((sys_baud16_i)&&(clk_cnt == 'd15))?bit_cnt+1'd1:bit_cnt;
check_bit <=check_bit;end
END:begin
sys_data <= sys_data;
error <= error;
clk_cnt <= (sys_baud16_i)?clk_cnt+'d1:clk_cnt;
bit_cnt <= ((sys_baud16_i)&&(clk_cnt == 'd15))?bit_cnt+1'd1:bit_cnt;
check_bit <= check_bit;end
default:begin
sys_data <= sys_data;
error <= ;
clk_cnt <= 'd0;
bit_cnt <= 'd0;
check_bit <= EVEN;end
endcase
end
end //assign
assign uart_rx_error_o = error;
assign sys_data_o = sys_data;
assign uart_rx_idle_o = (c_st == IDLE)?'b1:1'b0;
assign uart_rx_ack_o = ((c_st == END) && (sys_baud16_i == 'b1) && (clk_cnt == 4'd15))?'b1:1'b0; endmodule
partIV:uart_tx_tsb.v
`timescale ns / ps
module uart_tx_tsb();
reg sys_clk;
reg sys_rst_n; reg [:] sys_data_i;
reg sys_wreq_i;
initial begin
sys_clk=;
sys_data_i=;
sys_wreq_i=;
sys_rst_n=;
# sys_rst_n=;
end always begin
# sys_clk=~sys_clk;end wire sys_baud16_o;
wire sys_baud_o; uart_baud u0(
.sys_clk( sys_clk ),
.sys_rst_n( sys_rst_n ),
.sys_baud16_o( sys_baud16_o ),
.sys_baud_o( sys_baud_o )
); wire uart_tx;
wire uart_idle_o;
wire uart_ack_o;
uart_tx u1(
.sys_clk( sys_clk ),
.sys_rst_n( sys_rst_n ),
.sys_baud_i( sys_baud_o ),
.sys_wreq_i( sys_wreq_i ),
.sys_data_i( sys_data_i ),
.uart_tx( uart_tx ),
.uart_idle_o( uart_idle_o ),
.uart_ack_o( uart_ack_o )
); always @ (posedge sys_clk) begin
if(sys_rst_n == 'b0) begin
sys_wreq_i <= ;
sys_data_i <= ;end
else if(uart_ack_o) begin
sys_wreq_i <= ;
sys_data_i <= sys_data_i + 'd1;end
else begin
sys_wreq_i <= ;
sys_data_i <= sys_data_i;end
end endmodule
partV:uart_rx_tsb.v
`timescale ns / ps
module uart_rx_tsb();
reg sys_clk;
reg sys_rst_n; reg [:] sys_data_i;
reg sys_wreq_i;
initial begin
sys_clk=;
sys_data_i=;
sys_wreq_i=;
sys_rst_n=;
# sys_rst_n=;
end always begin
# sys_clk=~sys_clk;end wire sys_baud16_o;
wire sys_baud_o; uart_baud u0(
.sys_clk( sys_clk ),
.sys_rst_n( sys_rst_n ),
.sys_baud16_o( sys_baud16_o ),
.sys_baud_o( sys_baud_o )
); wire uart_tx;
wire uart_tx_idle_o;
wire uart_tx_ack_o;
uart_tx u1(
.sys_clk( sys_clk ),
.sys_rst_n( sys_rst_n ),
.sys_baud_i( sys_baud_o ),
.sys_wreq_i( sys_wreq_i ),
.sys_data_i( sys_data_i ),
.uart_tx( uart_tx ),
.uart_tx_idle_o( uart_tx_idle_o ),
.uart_tx_ack_o( uart_tx_ack_o )
); always @ (posedge sys_clk) begin
if(sys_rst_n == 'b0) begin
sys_wreq_i <= ;
sys_data_i <= ;end
else if(uart_tx_ack_o) begin
sys_wreq_i <= ;
sys_data_i <= sys_data_i + 'd1;end
else begin
sys_wreq_i <= ;
sys_data_i <= sys_data_i;end
end wire uart_rx_idle_o;
wire uart_rx_ack_o;
wire uart_rx_error_o;
wire [:] sys_data_o;
uart_rx u2(
.sys_clk( sys_clk ),
.sys_rst_n( sys_rst_n ),
.uart_rx( uart_tx ),
.sys_baud16_i( sys_baud16_o ),
.uart_rx_idle_o( uart_rx_idle_o ),
.uart_rx_ack_o( uart_rx_ack_o ),
.uart_rx_error_o( uart_rx_error_o ),
.sys_data_o( sys_data_o )
);
endmodule