module sig_nojitter (

                     clock ,

                     rst_n ,

                     sig_in,

                     sig_out

                     );

 input             clock ,rst_n ;

 input             sig_in ;

 output     reg        sig_out ; 

 reg     [:]     sig_reg ;

 wire             sig_dy ;

 always @ (posedge clock or negedge rst_n)

     if (!rst_n)

             sig_reg     <= 'd0 ;

     else

             sig_reg     <= {sig_reg[:],sig_in} ;

 // 稳定判定

 assign sig_dy = (sig_reg[:] == sig_reg[:]) ? 'd1 : 1'd0 ; 

 always @ (posedge clock or negedge rst_n)

     if (!rst_n)

             sig_out     <= 'd0 ;

     else  if (sig_dy)

             sig_out<= sig_reg[] ; 

 endmodule