DO254 VHDL编码规范

Name

Phase

Title

DO254_VHDL.1122

Synthesis

Avoid assigning a signal multiple times in the same sequential path.

避免同一时序路径下对一个信号进行多次赋值

DO254_NETLIST.1141

Chip

Do not overload a wire with too many drivers.

禁止对同一信号线进行多源驱动

DO254_NETLIST.1142

Constraints general

Do not have simultaneously active drivers on one signal.

同一个信号禁止同时有两个及以上有效驱动器

DO254_NETLIST.1143_a

Chip

Use tri-states to control bidirectional bus mode.

使用三态控制双向总线

DO254_NETLIST.1143_b

Chip

Only tri-state elements should be connected to the bidirectional buses.

只有三态逻辑可连接到双向总线上

DO254_NETLIST.1211

Constraints clocks

Do not use gated clocks (FPGA).

不适用门控时钟(FPGA

DO254_NETLIST.1212_a

Constraints clocks

Isolate gated clocks to a separate clock generator instance.

门控时钟应独立设计为一个时钟生成模块

DO254_NETLIST.1212_b

Constraints clocks

Gated clocks can be used only at top level (ASIC).

只能在顶层使用门控时钟(ASIC

DO254_NETLIST.1221

Constraints clocks

Do not use flip-flop output as a clock.

不将触发器的输出作为时钟使用

DO254_NETLIST.1222

Constraints clocks

Do not connect clocks to anything other than flip-flop clock pins.

仅将时钟信号连接到触发器的时钟引脚

DO254_NETLIST.1231

Constraints resets

Do not connect resets to anything other than flip-flop reset pins.

仅将复位信号连接至触发器的复位引脚

DO254_NETLIST.1232_a

Chip

Do not use combinatorial logic in reset lines.

复位信号链路中不使用组合逻辑

DO254_NETLIST.1232_b

Constraints resets

Avoid internally generated resets.

避免使用内部产生的复位信号

DO254_NETLIST.1232_c

Constraints resets

Place the reset generator instance at the top-level of design hierarchy.

在顶层例化复位信号产生模块

DO254_NETLIST.1242

Constraints resets

A flip-flop inference should have one asynchronous control.

触发器应具有异步控制端口

DO254_NETLIST.1243

Constraints resets

Do not use the same signal as clock and reset.

不将一个信号同时用做时钟信号和复位信号

DO254_NETLIST.1244

Synthesis

Do not use resets with mixed polarity.

复位信号使用单一极性

DO254_NETLIST.1245

Synthesis

All registers should have a reset control.

所有寄存器都应具有复位控制端口

DO254_VHDL.1311

Parse

Use the 'std_logic_1164' standard package whenever it is possible.

尽量使用‘std_logic_1164’

DO254_VHDL.1312

Parse

Use the 'numeric_std' package instead of 'std_logic_arith' and 'std_logic_unsigned' packages.

使用'numeric_std'

尽量不使用'std_logic_arith' 'std_logic_unsigned'

DO254_VHDL.1313

Elaboration

Use 'std_logic' only for I/O ports.

仅对I/O端口使用 'std_logic'

DO254_VHDL.1314

Parse

Do not use unsafe data types inside architecture.

在结构体不使用不安全的数据类型

DO254_VHDL.1315

Parse

Specify range for objects of 'integer' data type.

'integer'数据类型对象须声明范围

DO254_VHDL.1316

Parse

Do not use the 'bit' data type.

禁止使用 'bit'数据类型

DO254_VHDL.1317

Parse

Do not use the 'enum_encoding' attribute for enumerations.

枚举对象禁止使用'enum_encoding'属性

DO254_VHDL.1318

Parse

Specify range for interface objects of 'std_logic_vector' data type.

' std_logic_vector '数据类型对象须声明位宽

DO254_VHDL.1321

Parse

Use descending range for one-dimensional objects.

使用降序声明一维数据对象的范围

DO254_VHDL.1322

Elaboration

Specify '0' as least significant bit for one-dimensional objects.

使用‘0’表示一维数据对象的最低位

DO254_VHDL.1323

Parse

Use simple signals only for non-constant indexing.

数据的非常量索引应使用简单的信号表示(索引不能使用表达式)

DO254_VHDL.1331

Parse

All declared objects should be used in the description.

声明的所有对象都应被使用

DO254_VHDL.1332

Elaboration

All declared signals should be used in the description.

声明的所有信号都应被使用

DO254_VHDL.1341

Parse

Use constants or generics instead of hard-coded numbers.

使用常量或者参量代替数字

DO254_VHDL.1342

Parse

Avoid Hard-Coded vector reset Assignments.

避免在复位中直接使用数字矢量(将复位值定义为常量或者参量)

DO254_VHDL.1411

Parse

Do not use ordered port connections.

端口映射禁止使用顺序映射

DO254_VHDL.1412

Parse

Match port and connected signal names.

匹配信号名称及所连接的端口名称

DO254_VHDL.1421

Parse

Avoid unconnected input ports in component instance.

例化时,避免模块输入端口悬空

DO254_VHDL.1422

Parse

Avoid unconnected output ports in component instance.

例化时,避免模块输出端口悬空

DO254_NETLIST.1511

Constraints clocks

Do not use a clock signal as a data.

禁止将时钟信号用为数据

DO254_VHDL.1615

Elaboration

Avoid mismatching in assignment ranges.

避免赋值两端范围不匹配

DO254_VHDL.1621

Elaboration

Match bit widths of relational operator arguments.

条件运算符两边的数据位宽应匹配

DO254_VHDL.1633

Elaboration

Bit widths of component port and bind signal should match.

例化时,信号及其连接的端口数据位宽应匹配

DO254_VHDL.1711

Synthesis

Define all the necessary signals in the sensitivity list.

敏感列表包含所有必需的信号

DO254_VHDL.1721

Synthesis

Do not define unnecessary objects in the sensitivity list.

禁止敏感列表中包含非必需的信号

DO254_VHDL.1722

Synthesis

Do not use a signal within the same process statement it was assigned.

不在信号赋值的过程中使用该信号

DO254_VHDL.1811

Parse

Do not read global signals in a function body.

函数中不适用全局信号

DO254_VHDL.1812

Synthesis

Function return value should be defined in all the possible cases.

函数的返回值在任何条件下都应是确定的

DO254_VHDL.1821

Parse

A function should return at the end of its body.

函数应在其函数体的结尾处返回

DO254_VHDL.1822

Parse

Function should not return in conditional branches.

禁止函数在条件语句分支中返回

DO254_VHDL.1911

Synthesis

Use proper encoding type for FSM states.

有限状态机使用合适的编码

DO254_VHDL.1912

Synthesis

Use constants to define FSM state vectors.

使用常量定义有限状态机的向量

DO254_VHDL.1921

Synthesis

Each FSM should have reset control.

每一个有限状态机都应具有复位控制

DO254_VHDL.1922

Synthesis

All illegal or undefined states should transition to a defined state in a case of state corruption.

有限状态机应具备从非法或未定义状态中自动跳转到定义的状态中

DO254_VHDL.1923

Synthesis

Avoid unreachable states in FSM descriptions.

避免有限状态机中包含不可达状态

DO254_VHDL.1924

Synthesis

Avoid deadlock states in FSM descriptions.

避免有限状态机中死锁状态

DO254_NETLIST.1925

Chip

All FSM inputs should be synchronous to the state machine clock.

所有有限状态机的输入都应利用其主时钟进行同步后使用

DO254_NETLIST.2112

Chip

Port description order should follow a pattern.

端口定义顺序应服从某一模式

DO254_VHDL.2121_a

Parse

Do not describe multiple statements in one line.

禁止一行中包含多条语句

DO254_VHDL.2121_b

Parse

Do not describe multiple association elements in one line.

禁止一行中包含多个元素

DO254_VHDL.2121_c

Parse

Do not describe multiple declarations per line.

禁止一行中包含多个声明

DO254_VHDL.2122

Parse

Label statements whenever it is possible.

尽量对语句进行标识

DO254_VHDL.2123

Parse

Always use ending label or constructs name at the end of the statements and declarations.

在语句和声明的结尾处使用标识

DO254_VHDL.2124

Parse

Do not use the same names for different objects.

禁止对不同对象使用同一名称

DO254_VHDL.2125

Parse

Indent each level of the source code.

代码逐层缩进

DO254_VHDL.2126

Parse

Use spaces instead of tabs.

使用空格,而不使用占位符

DO254_VHDL.2131

Parse

Avoid large design files.

避免单一设计过大

DO254_VHDL.2132

Parse

Describe one design unit per file.

每一个设计文件仅包含一个设计模块

DO254_VHDL.2141

Parse

Ensure consistent file header.

确保一致的文件头注释

DO254_VHDL.2142

Parse

Ensure sufficient comment density.

确保充足的注释

DO254_VHDL.2143

Parse

Ensure commenting of design constructs.

确保设计结构具有注释

DO254_VHDL.2221

Parse

Do not describe same objects using both upper and lower letter case.

禁止同一对象一处使用大写,在另一处使用小写(同一对象名称应大小写保持不变)

DO254_VHDL.3111

Elaboration

Do not use multiple waveform and optional delay expression in assignments.

禁止在赋值中使用多个波形和可选的延迟表达式

DO254_VHDL.3121

Parse

Avoid using records in RTL description.

禁止在寄存器传输级设计中使用records

DO254_VHDL.3131

Synthesis

Do not use register initialization assignments.

禁止对寄存器定义时赋初值

DO254_VHDL.3141

Synthesis

Avoid Undriven Signals.

禁止未经驱动的信号

DO254_NETLIST.3151

Constraints general

Avoid long combinational paths.

禁止长组合逻辑路径

DO254_VHDL.3152

Parse

Limit the use of nested 'if' and 'case' statements.

限制ifcase语句的嵌套级数

DO254_VHDL.3212

Parse

Case statement should always have 'others' choice.

Case语句必须包含others分支

DO254_VHDL.3221

Synthesis

Do not describe unreachable conditions.

禁止包含不可达条件分支

DO254_VHDL.3223

Parse

Do not use 'with select' statement.

禁止使用’with select’语句

DO254_NETLIST.3411

Chip

Do not connect inout port directly to input/output ports.

禁止直接将inout端口连接至input或者output端口

DO254_NETLIST.3412

Constraints general

Avoid delay chains in digital logic.

禁止在数字逻辑中包含延时

DO254_NETLIST.3413

Constraints general

Associate each signal with only one non-tri-state driver.

每个信号仅使用一个非三态源进行驱动

DO254_NETLIST.3414

Constraints general

Avoid feed-throughs in digital logic.

避免在数字逻辑中使用输入输出直连

DO254_NETLIST.3511

Constraints general

Do not use combinatorial feedbacks.

禁止使用组合逻辑反馈

DO254_VHDL.3611

Elaboration

Do not describe multiple independent conditions in the process.

禁止在process中使用多个独立的条件

DO254_NETLIST.3621

Constraints general

Avoid latches as much as possible.

尽量避免使用锁存器

DO254_NETLIST.3631

Chip

Each register should be controllable from its inputs.

应能从外部输入引脚控制每个寄存器

DO254_VHDL.3641

Synthesis

Avoid using variables to infer sequential logic.

避免时序逻辑中使用变量

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