`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer: chensimin

//

// Create Date: 2018/05/23 16:14:30

// Design Name:

// Module Name: uart_rx

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module uart_rx(

    input  wire  clk,

    input  wire  rxd,

    output reg   [:]data_i,

    output wire  receive_ack

    );

    reg [:] data_i = ;

    localparam     IDLE = ,

                   RECEIVE = ,

                   RECEIVE_END = ;

    reg [:]cur_st = ;

    reg [:]nxt_st = ;

    always @(posedge clk)

    begin

        cur_st <= nxt_st;

    end

    always @(*)

    begin

        nxt_st = cur_st;

        case(cur_st)

           IDLE:

           begin

                   if(!rxd)                  //当从接收端口上进来的数据开始为0时，即启动接收

                       nxt_st = RECEIVE;

           end

           RECEIVE:

           begin

                   if(count == )

                       nxt_st = RECEIVE_END;

           end

           RECEIVE_END:

           begin

                   nxt_st = IDLE;

           end

           default:

           begin

                   nxt_st = IDLE;

           end

        endcase

    end

    reg [:]count = ;

      always @(posedge clk)

      begin

        if(cur_st == RECEIVE)

            count <= count + ;

          else if(cur_st == IDLE || cur_st == RECEIVE_END)

            count <= ;

    end

    //当前状态为接收状态时，rxd 信号线上的数据存储在data_i的最高位

    //同时data_i 的数据总体右移一位

      always @(posedge clk)

      begin

          if(cur_st == RECEIVE)

          begin

             data_i[:] <= data_i[:];

             data_i[] <= rxd;            // rxd 传过来什么数据， data_i上立马显示什么数据，因为是从端口采集到的数据

          end

      end

    assign receive_ack = (cur_st == RECEIVE_END) ? : ;

endmodule

/*

add_force {/uart_rx/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps

add_force {/uart_rx/rxd} -radix hex {1 0ns} {0 300ns} {1 400ns} {0 500ns} {1 600ns} {0 700ns} {1 800ns} {0 900ns} {1 1000ns}

*/