//////////////////////////////////////////////////////////////////////////////////
//
// The ZYNQ FIFO slave settings:
// - implements write state machine for 32-bit addressable AXI slave
// - provides settings for state of per-stream fifo pointers
// - implements configuration of FIFO's physical DDR addresses
////////////////////////////////////////////////////////////////////////////////// module zf_slave_settings
#(
parameter CONFIG_BASE = 'h40000000
)
(
input clk,
input rst, //------------------------------------------------------------------
//-- control write signals - slave
//------------------------------------------------------------------
input [:] AXI_AWADDR,
input AXI_AWVALID,
output AXI_AWREADY,
input [:] AXI_WDATA,
input [:] AXI_WSTRB,
input AXI_WVALID,
output AXI_WREADY,
output [:] AXI_BRESP,
output AXI_BVALID,
input AXI_BREADY, //------------------------------------------------------------------
// settings interface
//------------------------------------------------------------------
output reg [:] addr,
output reg [:] data,
output strobe, output [:] debug
); ////////////////////////////////////////////////////////////////////////
///////////////////////////// Begin R T L //////////////////////////////
//////////////////////////////////////////////////////////////////////// //------------------------------------------------------------------
// Control write state machine responds to AXI control writes
// Used for setting the state of the various FIFOs
//------------------------------------------------------------------
localparam STATE_ADDR = ;
localparam STATE_DATA = ;
localparam STATE_WRITE = ; reg [:] state; always @(posedge clk) begin
if (rst) begin
state <= STATE_ADDR;
addr <= ;
data <= ;
end
else case (state) STATE_ADDR: begin
if (AXI_AWVALID && AXI_AWREADY) begin
addr <= (AXI_AWADDR - CONFIG_BASE);
state <= STATE_DATA;
end
end STATE_DATA: begin
if (AXI_WVALID && AXI_WREADY) begin
data <= AXI_WDATA;
state <= STATE_WRITE;
end
end STATE_WRITE: begin
state <= STATE_ADDR;
end default: state <= STATE_ADDR; endcase //state
end assign strobe = (state == STATE_WRITE); //assign to slave write
assign AXI_AWREADY = (state == STATE_ADDR);
assign AXI_WREADY = (state == STATE_DATA);
assign AXI_BRESP = ;
assign AXI_BVALID = AXI_BREADY; //FIXME - we can choose not to assert valid endmodule //zf_slave_settings
配合使用的RTL代码如下
//----------------------------------------------------------------------
//-- A settings register is a peripheral for the settings register bus.
//-- When the settings register sees strobe abd a matching address,
//-- the outputs will be become registered to the given input bus.
//---------------------------------------------------------------------- module setting_reg
#(parameter my_addr = ,
parameter awidth = ,
parameter width = ,
parameter rst_idel=)
(input clk, input rst, input strobe, input wire [awidth-:] addr,
input wire [:] in_data,
output reg [width-:] out_data, output reg changed); always @(posedge clk)
if(rst)
begin
out_data <= rst_idel;
changed <= 'b0;
end
else
if(strobe & (my_addr==addr))
begin
out_data <= in_data[width-:];
changed <= 'b1;
end
else
changed <= 'b0; endmodule // setting_reg