The I2C-bus specification(V2.1)摘要

尽量保持原文,但为了让摘要更简洁,个人做了小小的更改。

1.10-bit addressing allows 1024 additional slave addresses.

2.The High-speed mode allows an increase in the bit rate up to 3.4 Mbit/s.

3.The Fast-mode allows a fourfold increase of bit rate-up to 400 kbit/s.

4.Fast-mode devices are downwards compatible i.e. they can be used in a 0 to 100 kbit/s I2C-bus system.

5.Each device connected to the bus is software addressable

6.masters can operate as master-transmitters or as master-receivers

7.It's true multi-master bus including collision detection and arbitration to prevent data corruption

8.Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard-mode

9.I2C-bus interface is already integrated on-chip.

10.The simple 2-wire serail I2C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks.

11.

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