模块示意图如下：

端口配置清单：

verilog 代码：

module counter(
	clock,
	reset,
	enable,
	count);

	input clock;
	input reset;
	input enable;
	output [3:0] count;

	wire clock;
	wire reset;
	wire enable;
	reg [3:0] count;

	always @ (posedge clock) 
	begin 
		if (reset == 1) 
		begin 
			count <= 0;
		end
		else if (enable == 1) 
		begin 
			count <= count + 1; 
		end 
	end
	
endmodule 

在 always 语句块中，修改 reg 端口的值要用 <= 符号。

测试代码如下：

module counter_test();

	reg clock;
	reg reset;
	reg enable;
	wire [3:0] result;

	initial begin
		clock = 1;
		reset = 0;
		enable = 0;
		#5 reset = 1;
		#10 reset = 0;
		#10 enable = 1;
		#150 enable = 0;
		#5 $finish;
	end
	always begin
		#5 clock = ~clock;
	end
	
	initial begin
		$dumpfile ("... .../counter_test.vcd");
		$dumpvars;
	end

	counter counter1(
		.clock(clock),
		.reset(reset),
		.enable(enable),
		.count(result));

endmodule 

测试一下，看看波形图：

比较一下代码，和预期一样呀，真不错！