因为目录Verilog Language-Combinational Logic下的练习题有点多,我还没做完,今天先发Basic Gates与Multiplexers下的。
Basic Gates
in_out
module top_module ( input in, output out); assign out = in ; endmodule
Exams/m2014 q4i
module top_module ( output out); assign out = 1'b0; endmodule
Exams/m2014 q4e
module top_module ( input in1, input in2, output out); assign out = ~(in1|in2); endmodule
Exams/m2014 q4f
module top_module ( input in1, input in2, output out); assign out = (~in2)&in1; endmodule
Exams/m2014 q4g
module top_module ( input in1, input in2, input in3, output out); assign out = (~(in1^in2))^in3; endmodule
Gates
module top_module( input a, b, output out_and, output out_or, output out_xor, output out_nand, output out_nor, output out_xnor, output out_anotb ); assign out_and =a&b; assign out_or =a|b; assign out_xor =a^b; assign out_nand =~(a&b); assign out_nor =~(a|b); assign out_xnor =~(a^b); assign out_anotb=a&~b; endmodule
7420
module top_module ( input p1a, p1b, p1c, p1d, output p1y, input p2a, p2b, p2c, p2d, output p2y ); assign p1y = ~(p1a&p1b&p1c&p1d); assign p2y = ~(p2a&p2b&p2c&p2d); endmodule
Truthtable1
module top_module( input x3, input x2, input x1, output f ); assign f = ( ~x3 & x2 & ~x1 ) | ( ~x3 & x2 & x1 ) | ( x3 & ~x2 & x1 ) | ( x3 & x2 & x1 ) ; endmodule
Mt2015 eq2
module top_module ( input [1:0] A, input [1:0] B, output z ); assign z=(A==B)?1'b1:1'b0; endmodule
Mt2015 q4a
module top_module (input x, input y, output z); assign z = (x^y) & x; endmodule
Mt2015 q4b
module top_module ( input x, input y, output z ); assign z=~(x^y); endmodule
Mt2015 q4
module top_module (input x, input y, output z); wire z13,z24; wire zor,zand; assign z13 = (x^y) & x; assign z24 = ~(x^y); assign zor = z13|z24; assign zand =z13&z24; assign z =zor ^zand; endmodule
Ringer
module top_module ( input ring, input vibrate_mode, output ringer, output motor ); assign ringer = ring & ~vibrate_mode; assign motor = ring & vibrate_mode; endmodule
Thermostat
module top_module ( input too_cold, input too_hot, input mode, input fan_on, output heater, output aircon, output fan ); assign heater = mode & too_cold; assign aircon = ~mode & too_hot; assign fan = heater|aircon|fan_on; endmodule
Popcount3
module top_module( input [2:0] in, output [1:0] out ); assign out[0] = (~in[2] & ~in[1] & in[0]) | (~in[2] & in[1] & ~in[0]) | (in[2] & ~in[1] & ~in[0]) | (in[2] & in[1] & in[0]); assign out[1] = (in[1] & in[0]) | (in[2] & in[0]) | (in[2] & in[1]); endmodule
Gatesv
module top_module( input [3:0] in, output [2:0] out_both, output [3:1] out_any, output [3:0] out_different ); assign out_both = in[3:1] & in[2:0]; assign out_any = in[3:1] | in[2:0]; assign out_different = {in[0], in[3:1]} ^ in; endmodule
Gatesv100
module top_module( input [99:0] in, output [98:0] out_both, output [99:1] out_any, output [99:0] out_different ); assign out_both = in[99:1] & in[98:0]; assign out_any = in[99:1] | in[98:0]; assign out_different = {in[0], in[99:1]} ^ in; endmodule
Multiplexers
Mux2to1
module top_module( input a, b, sel, output out ); assign out = (sel)? b:a; endmodule
Mux2to1v
module top_module( input a, b, sel, output out ); assign out = (sel)? b:a; endmodule
Mux9to1v
module top_module( input [15:0] a, b, c, d, e, f, g, h, i, input [3:0] sel, output [15:0] out ); always @(*)begin case(sel) 4'd0:out = a ; 4'd1:out = b ; 4'd2:out = c ; 4'd3:out = d ; 4'd4:out = e ; 4'd5:out = f ; 4'd6:out = g ; 4'd7:out = h ; 4'd8:out = i ; default:out = 16'hffff; endcase end endmodule
Mux256to1
module top_module( input [255:0] in, input [7:0] sel, output out ); assign out = in[sel]; endmodule
Mux256to1v
module top_module( input [1023:0] in, input [7:0] sel, output [3:0] out ); assign out = in[sel*4+:4]; endmodule