always @ (posedge clk or negedge resetn)  
    if (!resetn) r_vsync <= `SD 1'b0;   
    else         r_vsync <= `SD vsync;
wire vsync_fe = (!vsync)&r_vsync;

always @ (posedge clk or negedge resetn)begin
     if (!resetn) 
         xxxx;
     else if (vsync_fe)
         xxx <= xxx;
end