//---------------------
// 奇数分频
//Author：陈泉秀
//---------------------
//实现5分频
module	clk_odd_divider
(
input			clk,
input			rst_n,
output			clk_out
);
reg		[2:0]	count;
reg				clk_p;
reg				clk_n;

always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			count	<=	3'd0;
		else if(count == 3'd4) //0-4
			count	<=	3'd0;
		else
			count	<=	count + 1'b1;
	end
	
always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			clk_p	<=	1'b0;
		else if((count==3'd2)||(count==3'd4))
			clk_p	<=	~clk_p;
	end

always@(negedge clk or negedge rst_n)
	begin
		if(!rst_n)
			clk_n	<=	1'b0;
		else if((count==3'd2)||(count==3'd4))
			clk_n	<=	~clk_n;
	end
	
assign	clk_out	=	clk_n|clk_p;

endmodule

//----------------
// Author: chenquanxiu
//-------------------
`timescale	1ns/1ns
module	clk_odd_divider_tb;
reg	clk;
reg rst_n;
reg data;
wire detector_out;

initial
	begin
		clk		=	1'b0;
		rst_n	=	1'b1;
	#10	rst_n	=	1'b0;
	#30	rst_n	=	1'b1;
	end
	
	always	#5	clk = ~clk;
	
clk_odd_divider
A(
			clk,
			rst_n,
			clk_out
);

endmodule