//上升沿检测电路，打一拍后，看前后是否相反

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		a_ff0 <= 1'b0;
	end
	else begin
		a_ff0 <= a;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		pedge <= 1'b0;
	end
	else if(a==1'b1&&a_ff0==1'b0) begin		
		pedge <= 1'b1;
	end
	else begin
		pedge <= 1'b0;
	end
end