时钟和频率

1KHZ     1ms      1毫秒

1MHZ     1us       1微秒

1GHZ      1ns       1纳秒

1s = 10（3）ms    =  10（6）us    = 10（9）ns

复位

同步复位：按下复位键后，等待时钟上升沿后复位才有效

异步复位：复位键有效后即复位，与时钟沿无关

 

//CHN: 异步上沿复位
always @ (posedge clk or posedge rst) begin
    if (rst) begin
        
//CHN: 异步下沿复位
always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        
//CHN: 同步上沿复位
always @ (posedge clk) begin
    if (rst) begin
        
//CHN: 同步下沿复位
always @ (posedge clk) begin
    if (~rst_n) begin

 

always @ (posedge clk) begin
    if (rst) begin
        r_data_valid    <= 1'b0;
    end else begin
        r_data_valid    <= i_data_valid;
    end
end

always @ (posedge clk) begin
    r_data_valid_4ff    <= {r_data_valid_4ff[2:0],r_data_valid};
end

always @ (posedge clk) begin
    if (rst) begin
        r_out_valid <= 1'b0;
    end else begin
        r_out_valid <= r_data_valid_4ff[3];
    end
end

 

通过波形图可以看出r_out_valid的波形图有问题，不能达到复位的目的，修改的办法有两种：1.rst有效拉长8拍    2 r_data_valid[1]  r_data_valid[.2]  r_data_valid[3]都复位

 

always @ (posedge clk) begin
    if (rst) begin
        r_data_valid    <= 1'b0;
    end else begin
        r_data_valid    <= i_data_valid;
    end
end

always @ (posedge clk) begin
    if (rst) begin
        r_data_valid_4ff <= 4'b0000; 
    end else begin
    r_data_valid_4ff    <= {r_data_valid_4ff[2:0],r_data_valid};
    end
end

always @ (posedge clk) begin
    if (rst) begin
        r_out_valid <= 1'b0;
    end else begin
        r_out_valid <= r_data_valid_4ff[3];
    end
end

宏定义文件

宏定义文件放在sources_1文件夹下，内容如下：

//
// Copyright (c) 2020 Kikyoko
// https://github.com/Kikyoko
// 
// Module   : FPGA_DEFINE
// Device   : Xilinx/Altera
// Author   : Kikyoko
// Contact  : Kikyoko@outlook.com
// Date     : 2020/12/9 19:13:35
// Revision : 1.00 - Simulation correct
//
// Description  : fpga define file
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//

// =========================================================================================================================================
// Project
// =========================================================================================================================================
`timescale 1ns/1ps

`define _DEVICE_XILINX
//`define _DEVICE_ALTERA

`define _USE_URAM

// =========================================================================================================================================
// Parameter
// =========================================================================================================================================
`define _image_width    1280
`define _image_height   720

`define _gauss_width    1280
`define _gauss_height   360

`define _COST_TH        12
`define _thresh         15
`define _p1             10
`define _configInt_12   5
`define _configInt_16   20
`define _configInt_17   20

`timescale 1ns/1ps

`timescale是指定仿真的时间单位和精度，当前设置为单位1ns，精度1ps。

`define _DEVICE_XILINX

定义当前使用器件是XILINX ，目前的器件为XILINX 和ATERA器件

时序约束

时钟约束文件timing.xdc文件放在constrs_1文件夹下

## hard clock
create_clock -period 20.000 -name hard_clk [get_ports hard_clk]

create_clock：创建一个时钟

-period 20.000：此时钟的周期为20ns
-name hard_clk：此时钟的名字为hard_clk
[get_ports hard_clk]：此时钟接在了管脚hard_clk上