单bit跨时钟域脉冲同步器，快时钟域到慢时钟域脉冲同步

模块

module mul_clk(
input       clk_a   ,
input       clk_b   ,
input       rst_n   ,
input       din     ,
output reg dout
);

reg din_dely = 0;
reg feedback = 0;
	
always@(posedge clk_a or negedge rst_n)
begin
	if(