module reset_sync

  (input clk,

   input reset_in,

   output  reset_out);

   (* ASYNC_REG = "TRUE" *) reg reset_int = 'b1;

   (* ASYNC_REG = "TRUE" *) reg reset_out_tmp = 'b1;

   always @(posedge clk or posedge reset_in)

     if(reset_in)

       {reset_out_tmp,reset_int} <= 'b11;

     else

       {reset_out_tmp,reset_int} <= {reset_int,'b0};

   assign reset_out = reset_out_tmp;

endmodule // reset_sync