设计部分：4位计数器（边沿触发）

以下代码：

module count（clk, reset, cnt);
  input clk, reset;
  output[4:0] cnt;

  reg[4:0] cnt;
  always @(posedge clk) begin
    if(reset)
      cnt <= 0; //同步复位
    else
      cnt <= cnt+1'b1; //计数
  end  
endmodule

验证部分

以下代码：

`timescale 1ns/1ns
module test;
  /*Make a reset that pulses once.*/
  reg clk=0, reset = 0;
  wire[3:0] out;
  
  always #20 clk = ~clk;   

  count4 ctr(out,reset,clk);

  initial begin
    #2  reset = 1;        //reset
    #3  reset = 0;        //start count
    #24 reset = 1;        //reset
    #2  reset = 0;        //start count
    #48 reset = 1;        //reset
    #1  reset = 0;        //start count
    #60 reset = 1;        //reset
    #3  reset = 0;        //start count
    #100 $stop;
  end 
        
  initial begin            
    $fsdbdumpfile("test.fsdb");
    $fsdbdumpvars("+all");  //dump all signal
  end
endmodule