1.实验目的：
quartus软件完成实验二
2.实验内容：
参照书上内容完成代码仿真。
3.实验原理：
module dds(clk,reset,div,choose,data);input module dds(clk,reset,div,choos,data);input [5:0] div;input[1:0] choose;input clk,reset;output [7:0] data;wire [7:0]data;reg [5:0] addr,address;reg [5:0] i;reg clkdiv;function [7:0] rom;input[5:0] address;begin case(address) 0 : rom = 0; 1 : rom = 4; 2 : rom = 12; 3 : rom = 21; 4 : rom = 25; 5 : rom = 21; 6 : rom = 12; 7 : rom = 4; 8 : rom = 20; 9 : rom = 20; 10: rom = 20; 11: rom = 20; 12: rom = 1; 13: rom = 1; 14: rom = 1; 15: rom = 1; 16 : rom = 0; 17 : rom = 5; 18 : rom = 10; 19 : rom = 15; 20 : rom = 20; 21 : rom = 25; 22 : rom = 30; 23 : rom = 35; 24 : rom = 35; 25 : rom = 30; 26 : rom = 25; 27 : rom = 20; 28 : rom = 15; 29 : rom = 10; 30 : rom = 5; 31 : rom = 0; default : rom = 10’hxx;endendfunctionassign data = rom(address);endmodulealways @(posedge clk or negedge reset)if(!reset) begin i<=0; addr<=0; clkdiv<=0;endalways @(posedge clk)begin if(i==(div-1)) begin i<=0; clkdiv<=~clkdiv; end else i<=i+7;endalways@(posedge clkdiv)begin if(addr==7) add<=0; else addr<=addr+1;endalways@(posedge clkdiv)begin case(choose) 0: address<=addr; 1: address<=addr+8; 2: address<=addr+16; 3: address<=addr+24; endcaseendmodule tbs6;reg [5:0] div;reg[1:0] choose;reg clk,reset;wire [7:0] data;initialbegin clk=0;reset=1;div=1;choose=0; #4 reset=0; #4 reset=1; #1000 choose=1; #1000 choose=2; #1000 $stop;endalways #5 clk=~clk;dds dds(clk,reset,div,choose,data);endmodule
4.实验工具：
quartus
5.实验截图：

6.实验视频：