`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date:    15:09:32 06/13/2017

// Design Name:

// Module Name:    inv_cordivision

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module inv_cordivision

#(

    parameter DATA_SIZE    = ,

    parameter PIPELINE_LEN =

)

(

    input                    clk,

    input                    nd,

    input [DATA_SIZE- : ]  x_in,

    input [DATA_SIZE- : ]  y_in,

    input [DATA_SIZE- : ]  z_in,

    output                   rdy,

    output[DATA_SIZE- : ]  x_out,

    output[DATA_SIZE- : ]  y_out,

    output[DATA_SIZE- : ]  z_out

);

generate

    wire                           rdy_temp       [PIPELINE_LEN : ];

    wire [DATA_SIZE- : ]     x_temp        [PIPELINE_LEN : ];

    wire [DATA_SIZE- : ]     y_temp        [PIPELINE_LEN : ];

    wire [DATA_SIZE- : ]     z_temp        [PIPELINE_LEN : ];

    assign rdy_temp[]   = nd;

    assign x_temp[]     = x_in;

    assign y_temp[]     = y_in;

    assign z_temp[]     = z_in;

    assign rdy               = rdy_temp[PIPELINE_LEN];

    assign x_out           = x_temp[PIPELINE_LEN];

    assign y_out           = y_temp[PIPELINE_LEN];

    assign z_out           = z_temp[PIPELINE_LEN];

    genvar i;

        for(i=;i<(PIPELINE_LEN);i=i+)

            begin : unit

                inv_cordivision_unit

                #(

                    .DATA_SIZE    ( DATA_SIZE   ),

                    .FRAC_SIZE  ( DATA_SIZE- ),

                    .LEVEL        (    i  )

                )

                i2

                (

                    .clk(clk),            

                    .nd(rdy_temp[i]),

                    .x_in(x_temp[i]),

                    .y_in(y_temp[i]),

                    .z_in(z_temp[i]),                    

               .rdy(rdy_temp[i+]),

                    .x_out(x_temp[i+]),

                    .y_out(y_temp[i+]),

                    .z_out(z_temp[i+])

                );

            end

endgenerate

endmodule

module inv_cordivision_unit

#(

    parameter DATA_SIZE = ,

    parameter FRAC_SIZE = ,

    parameter LEVEL     =

)

(

    input                                             clk,

    input                                            nd,

    input      signed     [DATA_SIZE-:]       x_in,

    input      signed     [DATA_SIZE-:]       y_in,

    input      signed     [DATA_SIZE-:]       z_in,

    output reg                                         rdy,

    output reg signed    [DATA_SIZE-:]     x_out,

    output reg signed    [DATA_SIZE-:]     y_out,

    output reg signed    [DATA_SIZE-:]     z_out

);

parameter[DATA_SIZE-:]  ONE = **(FRAC_SIZE);

reg signed [DATA_SIZE-:] x_w=,y_w=,z_w=;

        //时序逻辑

always @( posedge clk )begin

    rdy   <= nd;

    x_out <= x_w;

    y_out <= y_w;

     z_out <= z_w;

end

        //组合逻辑

always @( * )

    begin

        x_w = x_in;

        if( y_in[DATA_SIZE-] != x_in[DATA_SIZE-] )

            begin

                y_w = y_in + (x_in>>>(LEVEL));

                z_w = z_in - (ONE>>(LEVEL));

            end

        else

            begin

                y_w = y_in - (x_in>>>(LEVEL));

                z_w = z_in + (ONE>>(LEVEL));

            end

    end

endmodule

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date:   16:25:28 06/13/2017

// Design Name:   inv_cordivision

// Module Name:   F:/INV/ise/inv/inv_cordivision_tst.v

// Project Name:  inv

// Target Device:

// Tool versions:

// Description:

//

// Verilog Test Fixture created by ISE for module: inv_cordivision

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

////////////////////////////////////////////////////////////////////////////////

module inv_cordivision_tst;

    // Inputs

    reg clk;

    reg nd;

    reg [:] x_in;

    reg [:] y_in;

    reg [:] z_in;

    // Outputs

    wire rdy;

    wire [:] x_out;

    wire [:] y_out;

    wire [:] z_out;

    // Instantiate the Unit Under Test (UUT)

    inv_cordivision uut (

        .clk(clk),

        .nd(nd),

        .x_in(x_in),

        .y_in(y_in),

        .z_in(z_in),

        .rdy(rdy),

        .x_out(x_out),

        .y_out(y_out),

        .z_out(z_out)

    );

   parameter PERIOD = ;

   initial begin

      clk = 'b0;

      #(PERIOD/);

      forever

         #(PERIOD/) clk = ~clk;

   end

    initial begin

        // Initialize Inputs

        nd   <= ;

        x_in <= ;

        y_in <= ;

        z_in <= ;

        // Wait 100 ns for global reset to finish

        #;

        // Add stimulus here

        nd   <= ;

        x_in <= ;

        y_in <= ;

        z_in <= ;

    end

endmodule