Main.C时钟设定

void Main(void)

       时钟设定:400M 100M  50M    得到  1:4:8  进而需要得到 hdivn=2 ; pdivn=1;

i = 2 ;    //用于选择CUP核的频率;以及对应MPLL_vall ;key 参数;

switch ( i )

case 2: //400
                  key = 14;                                    key=14 指  hdivn_val (FCLK:HCLK) 1:4 ; hdivn=2
                  mpll_val = (92<<12)|(1<<4)|(1);   MPLL=2*(92+8)*12M/(1+2)*2^1=400M 
                  break;

//init FCLK=400M, so change MPLL first
 ChangeMPllValue((mpll_val>>12)&0xff, (mpll_val>>4)&0x3f, mpll_val&3);三个参数传递给rMPLLCON
 ChangeClockDivider(key, 12);                         12   指    (HCLK:PCLK)  1:2   ; pdivn=1
 cal_cpu_bus_clk();             400M 100M  50M    得到  1:4:8  进而得到 hdivn=2 ; pdivn=1;计算过程

 //*************************[ MPLL ]*******************************
void ChangeMPllValue(int mdiv,int pdiv,int sdiv)
{
rMPLLCON = (mdiv<<) | (pdiv<<) | sdiv; //根据频率需求推算各个参数,传递给rMPLLCON,总分总的程序模式
}
 // Modified for 2440.
void ChangeClockDivider(int hdivn_val,int pdivn_val)
{
int hdivn=, pdivn=; // hdivn_val (FCLK:HCLK)ratio hdivn
// 11 1:1 (0)
// 12 1:2 (1)
// 13 1:3 (3)
// 14 1:4 (2)
// pdivn_val (HCLK:PCLK)ratio pdivn
// 11 1:1 (0)
// 12 1:2 (1)
switch(hdivn_val) {
case : hdivn=; break;
case : hdivn=; break;
case :
case : hdivn=; break;
case :
case : hdivn=; break;
} switch(pdivn_val) {
case : pdivn=; break;
case : pdivn=; break;
} //Uart_Printf("Clock division change [hdiv:%x, pdiv:%x]\n", hdivn, pdivn);
rCLKDIVN = (hdivn<<) | pdivn; switch(hdivn_val) { 分频时钟在1:6或者1:8时,也会对摄像头时钟构成影响
case : // when 1, HCLK=FCLK/8.
rCAMDIVN = (rCAMDIVN & ~(<<)) | (<<);
break;
case : // when 1, HCLK=FCLK/6.
rCAMDIVN = (rCAMDIVN & ~(<<)) | (<<);
break;
} if(hdivn!=)
MMU_SetAsyncBusMode();
else
MMU_SetFastBusMode();
}
 static void cal_cpu_bus_clk(void)
{
U32 val;
U8 m, p, s; val = rMPLLCON;
m = (val>>)&0xff;
p = (val>>)&0x3f;
s = val&; //(m+8)*FIN*2 不要超出32位数!
FCLK = ((m+)*(FIN/)*)/((p+)*(<<s))*; val = rCLKDIVN;
m = (val>>)&;
p = val&;
val = rCAMDIVN;
s = val>>; switch (m) {
case :
HCLK = FCLK;
break;
case :
HCLK = FCLK>>;
break;
case :
if(s&)
HCLK = FCLK>>;
else
HCLK = FCLK>>;
break;
case :
if(s&)
HCLK = FCLK/;
else
HCLK = FCLK/;
break;
} if(p)
PCLK = HCLK>>;
else
PCLK = HCLK; if(s&0x10)
cpu_freq = HCLK;
else
cpu_freq = FCLK; val = rUPLLCON;
m = (val>>)&0xff;
p = (val>>)&0x3f;
s = val&;
UPLL = ((m+)*FIN)/((p+)*(<<s));
UCLK = (rCLKDIVN&)?(UPLL>>):UPLL;
}
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