1.main

/***************************** Include Files *********************************/

#include <stdio.h>

#include "xil_printf.h"

#include "xparameters.h"    /* XPAR parameters */
#include "xspi.h"        /* SPI device driver */
#include "xspi_l.h"
#include "xil_printf.h"

//#include "cdcm6208_spi.h"
#include "spi_drive.h"

#define CDCM_DEVICE_ID        XPAR_SPI_0_DEVICE_ID

int main()
{
    int byte_num = 4;
    u8 writeBuf[byte_num];
    u8 readBuf[byte_num];
    //read
    writeBuf[0] = 0x80;
    writeBuf[1] = 0x03;
    writeBuf[2] = 0x00;
    writeBuf[3] = 0x00;
    readBuf[0] = 0x00;
    readBuf[1] = 0x00;
    readBuf[2] = 0x00;
    readBuf[3] = 0x00;
    spi_trans(XPAR_SPI_0_BASEADDR ,0xfe, writeBuf,readBuf, byte_num);
    printf ("read_h is %x\n" ,readBuf[2]);
    printf ("read_l is %x\n" ,readBuf[3]);
    //write
    writeBuf[0] = 0x00;
    writeBuf[1] = 0x03;
    writeBuf[2] = 0x20;
    writeBuf[3] = 0xad;
    readBuf[0] = 0x00;
    readBuf[1] = 0x00;
    readBuf[2] = 0x00;
    readBuf[3] = 0x00;
    spi_trans(XPAR_SPI_0_BASEADDR ,0xfe, writeBuf,readBuf, byte_num);

    //read
    writeBuf[0] = 0x80;
    writeBuf[1] = 0x03;
    writeBuf[2] = 0x00;
    writeBuf[3] = 0x00;
    readBuf[0] = 0x00;
    readBuf[1] = 0x00;
    readBuf[2] = 0x00;
    readBuf[3] = 0x00;
    spi_trans(XPAR_SPI_0_BASEADDR ,0xfe, writeBuf,readBuf, byte_num);
    printf ("read_h is %x\n" ,readBuf[2]);
    printf ("read_l is %x\n" ,readBuf[3]);

    return 0;
}

2. "spi_drive.h"

#include "xil_io.h"

//AXI_Dual_SPI IPcore Reg addr
#define SPI_CR     0X60
#define SPI_SR     0X64
#define SPI_DTR     0X68
#define SPI_DRR     0X6C
#define SPI_SSR     0X70

#define GLO_IER     0X1C
#define IP_ISR     0X20
#define IP_IER     0X28
#define RESET     0X40

/*
 * Function name:   spi_trans(base_addr,slavedev_sel_bit,writeBufPtr,readBufPtr,byte_num)
 * Paramter :   base_addr: AXI quad spi IPcore base addrress
 *                 slavedev_sel_bit: chose slave device,default FF,only one bit low is choosed
 *                 writeBufPtr: wr {cmd,addr,data} to fifo,it is array,it name is pointer ofwriteBufPtr[0]
 *                 readBufPtr :the same
 *                 byte_num : the trans data bit / 8bit = byte_num
 */
void spi_trans(u32 base_addr ,u16 slavedev_sel_bit, u8 *writeBufPtr,u8 *readBufPtr,u16 byte_num)
{
    u8  data = 0;
    u8  i;
    u32 statereg;
//initial
    Xil_Out32((base_addr) + (0x40), (0x0000000A));//reset
    Xil_Out32((base_addr) + (0X1C),  0X80000000);//31bit-1,enab_intrupt
    Xil_Out32((base_addr) + (0X28), (0x00000004));//open the(SPI DTR)empty interpt
//disable trans
    Xil_Out32((base_addr + 0X60), 0X1E6);//000(1).1110.0110/(1)is dis_tran reset RX/TX FIFO
    Xil_Out32((base_addr + 0X60), 0X186);//000(1).1000.0110/(1)is dis_tran
//Write cmd&addr&data to fifo
    for(i=0; i<byte_num;i = i+1 )
    {
        data = *writeBufPtr;
        Xil_Out32((base_addr + 0X68), data);//trans to data trans reg
        writeBufPtr = writeBufPtr + 1;
    }
//choose slave_dev and trans
    Xil_Out32((base_addr + 0X70),(slavedev_sel_bit));//choose slave_dev, active low
    Xil_Out32((base_addr + 0X60), 0X086);//000(0).1(00)0.0110//start trans
//wait for trans to be done
    do{ statereg = Xil_In32((base_addr) + (0X64)); }
    while((statereg & 0x4)== 0);
//stop trans
    Xil_Out32((base_addr + 0x20), 0X00000004);//clear (SPI  DTR)is empty mask bit
    Xil_Out32((0x41E00000U) + (0X70), (0XFF));//disconnect slave_dev
    Xil_Out32((base_addr + SPI_CR), 0X186);//000(1).1000.0110//control 1 disab_tran
//read data
    for(i=0; i<byte_num;i = i+1 )
    {
        data = Xil_In32((base_addr) + (0X6C));
        *readBufPtr = data;
        readBufPtr = readBufPtr + 1;
    }

}