目录
4. Verification: Reading Simulations
4.2 Build a circuit from a simulation waveform
5. Verification: Writing Testbenches
4. Verification: Reading Simulations
4.1 Finding bugs in code
1. Mux
This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s).
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output[7:0] out );
assign out = sel?a: b;
endmodule2. NAND
You must use the provided 5-input AND gate:
module andgate ( output out, input a, input b, input c, input d, input e );
module top_module (input a, input b, input c, output out);//
wire out1;
andgate inst1 (out1, a, b, c,1'b1,1'b1);
assign out=~out1;
endmodule3. Mux
Nextbugs_addsubz
This 4-to-1 multiplexer doesn't work. Fix the bug(s).
You are provided with a bug-free 2-to-1 multiplexer:
module mux2 (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out ); //
wire [7:0]mux00, mux11;
mux2 mux0 ( sel[0], a, b, mux00 );
mux2 mux1 ( sel[1]&sel[0], c, d, mux11 );
mux2 mux21 ( sel[1], mux00, mux11, out );
endmodule4. Add/sub
The following adder-subtractor with zero flag doesn't work. Fix the bug(s).
// synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);//
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
if(out)
result_is_zero=1'b0;
else
result_is_zero=1'b1;
end
endmodule5. Case statement
This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. Fix the bug(s).
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid=1 );//
always @(*)begin
out='d0;
valid=1;
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3;
8'h25: out = 4;
8'h2e: out = 5;
8'h36: out = 6;
8'h3d: out = 7;
8'h3e: out = 8;
8'h46: out = 9;
default: valid = 0;
endcase
end
endmodule4.2 Build a circuit from a simulation waveform
给出时序波形图，根据信号波形写代码：
1. Combinational circuit 1
module top_module (
input a,
input b,
output q );//
assign q = a&&b; // Fix me
endmodule2. Combinational circuit 2
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = ~(a^b^c^d); // Fix me
endmodule3. Combinational circuit 3
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b&d | b&c | a&d | a&c; // Fix me
endmodule4. Combinational circuit 4
直接看很难得出结果，就用笨办法吧：直接画卡诺图进行求解。
module top_module (
input a,
input b,
input c,
input d,
output q );//
// assign q = (~a&b)|(a&b)|c; // Fix me
assign q=b|c;
endmodule
5. Combinational circuit 5
看仿真结果还是很容易就找到规律了。
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q );
always @(*)begin
case(c)
4'd0:q=b;
4'd1:q=e;
4'd2:q=a;
4'd3:q=d;
default: q=4'hf;
endcase
end
endmodule6. Combinational circuit 6
module top_module (
input [2:0] a,
output [15:0] q );
always@(*)begin
case(a)
3'd0:q=16'h1232;
3'd1:q=16'haee0;
3'd2:q=16'h27d4;
3'd3:q=16'h5a0e;
3'd4:q=16'h2066;
3'd5:q=16'h64ce;
3'd6:q=16'hc526;
3'd7:q=16'h2f19;
endcase
end
endmodule7. Sequential circuit 7
module top_module (
input clk,
input a,
output q );
always @(posedge clk)begin
if(a==1'b1)q<=1'b0;
else q<=1'b1;
end
endmodule8. Sequential circuit 8
module top_module (
input clock,
input a,
output p,
output q );
always @(*)begin
if(clock)p=a;
else p=p;
end
always @( negedge clock)begin
q<=p;
end
endmodule9. Sequential circuit 9
module top_module (
input clk,
input a,
output [3:0] q );
always@(posedge clk)begin
if(a)begin
q <= 4'd4;
end
else if(q == 4'd6)begin
q <= 4'd0;
end
else begin
q <= q + 1'b1;
end
end
endmodule10. Sequential circuit 10
module top_module (
input clk,
input a,
input b,
output q,
output state );
always@(posedge clk)begin
if(a == b)begin
state <= a;
end
end
always@(*)begin
q = a & ~b & ~state | ~a & ~b & state | a & b & state | ~a & b & ~state;
end
endmodule5. Verification: Writing Testbenches
1. Clock
时钟初始化和设置，tesetbench 中input 用reg，需要=赋值，output同wire，需要用assign赋值。
module top_module ( );
reg clk;
dut dut_inst(
.clk(clk)
);
/*
initial
begin
clk=0;
end
always begin
#5 clk=~clk;
end
*/
initial begin
clk=1'b0;
forever
#5 clk=~clk;
end
endmodule2. Testbench1
initial 语句只执行一次，always语言循环执行。
module top_module ( output reg A, output reg B );//
// generate input patterns here
initial begin
A=1'b0;
B=1'b0;
#10 A=1'b1;
#5 B=1'b1;
#5 A=1'b0;
#20 B=1'b0;
end
endmodule3. AND gate
module top_module();
reg [1:0]in;
wire out;
andgate andgate_inst(
.in(in),
.out(out)
);
initial begin
in=2'b00;
#10
in=2'b01;
#10
in=2'b10;
#10
in=2'b11;
end
endmodule4. Testbench2
module top_module();
reg clk;
reg in;
reg [2:0] s;
wire out;
q7 q7_inst(
.clk(clk),
.in(in),
.s(s),
.out(out)
);
initial begin
clk=1'b0;
s='d2;
in=1'b0;
#10
s='d6;
#10
s='d2;
in=1'b1;
#10
s='d7;
in=1'b0;
#10
s='d0;
in=1'b1;
#30
in=1'b0;
end
always begin
#5 clk=~clk;
end
endmodule5. T flip-flop
module top_module ();
reg clk;
reg reset;
reg t;
wire q;
tff tff_inst(
.clk(clk),
.reset(reset),
.t(t),
.q(q)
);
initial begin
reset=1'b1;
t=1'b0;
clk=1'b0;
#20
t=1'b1;
reset=1'b0;
end
always begin
#5 clk=~clk;
end
endmodule